rtlbrowse(1) [debian man page]

RTLBROWSE(1)							   File Viewing 						      RTLBROWSE(1)

NAME

       rtlbrowse - Allows hierarchical browsing of Verilog HDL sourcecode and library design files.

SYNTAX

       rtlbrowse <stemsfilename>

DESCRIPTION

       Allows  hierarchical browsing of Verilog HDL sourcecode and library design files.  Navigation through the hierarchy may be done by clicking
       open areas of the tree widget and clicking on the individual levels of hierarchy.  Inside the sourcecode, selecting the	module	instantia-
       tion  name by double clicking or selecting part of the name through drag-clicking will descend deeper into the RTL hierarchy.  Note that it
       performs optional source code annotation when called as a helper application by	gtkwave(1) and when the primary  marker  is  set.   Source
       code  annotation  is  not available for all supported dumpfile types.  It is directly available for LXT2, VZT, FST, and AET2.  For VCD, use
       the -o,--optimize option of gtkwave(1) in order to optimize the VCD file into FST.  All other dumpfile types (LXT, GHW) are unsupported	at
       this time.

EXAMPLES

       To run this program the standard way type:

       rtlbrowse stemsfile
	      The  RTL is then brought up in a GTK tree viewer.  Stems must have been previously generated with vermin(1) or some other tool capa-
	      ble of generating compatible stemsfiles.	Note that gtkwave(1) will bring up this program as a  client  application  for	sourcecode
	      annotation.  It does that by bringing up the viewer with the shared memory ID of a segment of memory in the viewer rather than using
	      a stems filename.

AUTHORS

       Anthony Bybell <bybell@rocketmail.com>

SEE ALSO

       vermin(1) gtkwave(1)

Anthony Bybell							      3.3.28							      RTLBROWSE(1)

VERMIN(1)							Verilog Compilation							 VERMIN(1)

NAME

       vermin - Parses and processes Verilog HDL files

SYNTAX

       vermin [VERILOGFILE]... [option]...

DESCRIPTION

       Parses Verilog HDL files for use by other tools.  The Verilog grammar used is 1364-1995.

OPTIONS

       -h[elp]
	      Prints out help screen.

       -emitmono fname
	      Emit monolithic (parser view of) file to fname.

       -emitstems
	      Emit source code stems to stdout.

       -emitvars
	      Emit source code variables to stdout.

       -Dx=y  Equivalent to `define X Y in source.

       +define+x=y
	      Equivalent to `define X Y in source.

       +incdir+dirname
	      Add dirname to include search path.

       +libext+ext
	      Add ext to filename when searching for files.

       -pragma name
	      Add  name (synopsys, verilint, vertex) to accepted pragmas.  Note that "vertex" is for legacy reasons; the executable name has since
	      changed to avoid name clashes with an existing 3D modeling program.

       -y dirname
	      Add directory dirname to source input path.

       -yi dirname
	      Add directory dirname to source input path (case insensitive search).

       -f filename
	      Insert args from filename.  Does not work recursively.

EXAMPLES

       The following indicates that the library extension is .v and that the include directory is the  current	working  directory  and  that  the
       library	directory  is  also the current working directory.  Stems generation is enabled to generate a stems file for use with other tools.
       Various compile-time defines are also defined on the command line.

       vermin XYZ450AC6V1.v -emitstems -y . +incdir+. +libext+.v -DUTLB_OutputData=0 -D__PORTALS_VERILOG__

AUTHORS

       Anthony Bybell <bybell@rocketmail.com>

SEE ALSO

       rtlbrowse(1) gtkwave(1)

Anthony Bybell							       0.1.1								 VERMIN(1)