simplifdczerobdd(3) [debian man page]

SIMPLIFDCZEROBDD(3)						   BDD functions					       SIMPLIFDCZEROBDD(3)

ORIGIN

       This  software  belongs	to  the  ALLIANCE CAD SYSTEM developed by the ASIM team at LIP6 laboratory of Universite Pierre et Marie CURIE, in
       Paris, France.

       Web : http://asim.lip6.fr/recherche/alliance/
       E-mail : alliance-users@asim.lip6.fr

NAME

       simplifDcZeroBdd - simplifies a BDD with don't cares on its off-set part

SYNOPSYS

       #include "logmmm.h"
       pNode simplifDcZeroBdd(pBdd1,pBdd2)
       pNode pBdd1;
       pNode pBdd2;

PARAMETERS

       pBdd1		   BDD to simplify

       pBdd2		   "don't care" function

DESCRIPTION

       simplifDcZeroBdd() simplifies pBdd1 with pBdd2. pBdd2 must be included imperatively in the off-set part of pBdd1. This function	returns  a
       BDD that depends to the order of the BDD.

EXAMPLE

       #include "mutnnn.h"	/* mbk utilities */
       #include "logmmm.h"
       pNode nodeA,NodeB;
       pNode res,res1,res2;

       initializeBdd(SMALL_BDD);
       nodeA = createNodeTermBdd(3);
       nodeB = createNodeTermBdd(3);
       res1 = applyBinBdd(OR,nodeA,nodeB);     /* res1 = (OR a b) */
       res2 = applyBinBdd(NOR,nodeA,nodeB);    /* res2 = (NOR a b) */
       res = simplifDcZeroBdd(res1,res2); /* res1 and res2 = 0 */
       displayBdd(res,1);

       /* it will display
       @res   ONE
       */

       destroyBdd(1);

SEE ALSO

       log(1),	bdd(1),  simplifDcOneBdd(3),  applyBdd(3),  notBdd(3), constraintBdd(3), applyBinBdd(3), addListBdd(3), displayBdd(3), createNode-
       TermBdd(3).

BUG REPORT

       This tool is under development at the ASIM department of the LIP6 laboratory.
       We need your feedback to improve documentation and tools.

ASIM
/LIP6							  October 1, 1997					       SIMPLIFDCZEROBDD(3)

GENLIB_SET_LORES(3)					       MBK LOGICAL FUNCTIONS					       GENLIB_SET_LORES(3)

NAME

       GENLIB_SET_LORES - set the resistance value of a logical resistor, after its creation.

ORIGIN

       This  software  belongs	to  the  ALLIANCE CAD SYSTEM developed by the ASIM team at LIP6 laboratory of Universite Pierre et Marie CURIE, in
       Paris, France.

       Web : http://asim.lip6.fr/recherche/alliance/
       E-mail : alliance-users@asim.lip6.fr

SYNOPSYS

       #include "mlo.h"

       void GENLIB_SET_LORES(figname,resname,newresi)
       char *figname ;
       char *resname ;
       double newresi ;

PARAMETERS

       figname		   Name of the logical figure

       resname		   Instance name of the resistor

       newresi		   New resistance value

DESCRIPTION

       GENLIB_SET_LORES looks in the list of resistors of the logical model figname for a resistor identified by its instance resname and set  the
       RESI field to the newresi value.

RETURN VALUE

       None

ERRORS

       "*** mbk error *** getlores impossible : resistor name doesn't exist in figure ptfig -> NAME"
	      No resistor matches the name.

EXAMPLE

       #include <genlib.h>

       int main(int argc,char *argv[])
       {
	 /* Create a figure to work on, a parallel resistor */
	 GENLIB_DEF_LOFIG("parallel_res") ;

	 /* Define interface */
	 GENLIB_LOCON("i",IN,"input") ;
	 GENLIB_LOCON("f",OUT,"output") ;

	 /* Add resistors */
	 GENLIB_LORES(RESMIM,5.1,"input","output","res1") ;
	 GENLIB_LORES(RESMIM,5.2,"input","output","res2") ;

	 /* Modify resistors value */
	 GENLIB_SET_LORES("parallel_res","res1",6.2) ;
	 GENLIB_SET_LORES("parallel_res","res2",6.3) ;

	 /* Save all that on disk */
	 GENLIB_SAVE_LOFIG() ;

	 return 0 ;
       }

SEE ALSO

       mbk(1), GENLIB_DEF_LOFIG(3), GENLIB_LORES(3)

BUG REPORT

       This tool is under development at the ASIM department of the LIP6 laboratory.
       We need your feedback to improve documentation and tools.

ASIM
/LIP6							  August 14, 2002					       GENLIB_SET_LORES(3)