verilog::netlist::interface(3pm) [debian man page]

Netlist::Interface(3pm) 				User Contributed Perl Documentation				   Netlist::Interface(3pm)

NAME

       Verilog::Netlist::Interface - Interface within a Verilog Netlist

SYNOPSIS

	 use Verilog::Netlist;

	 ...
	 my $interface = $netlist->find_interface('name');
	 my $cell = $self->find_cell('name')
	 my $port =  $self->find_port('name')
	 my $net =  $self->find_net('name')

DESCRIPTION

       A Verilog::Netlist::Interface object is created by Verilog::Netlist for every interface in the design.

ACCESSORS

       See also Verilog::Netlist::Subclass for additional accessors and methods.

       $self->comment
	   Returns any comments following the definition.  keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained.

       $self->find_port_by_index
	   Returns the port name associated with the given index.

       $self->modports
	   Returns list of references to Verilog::Netlist::ModPort in the interface.

       $self->modports_sorted
	   Returns list of references to Verilog::Netlist::ModPort in the interface sorted by name.

       $self->name
	   The name of the interface.

       $self->netlist
	   Reference to the Verilog::Netlist the interface is under.

       $self->nets
	   Returns list of references to Verilog::Netlist::Net in the interface.

       $self->nets_sorted
	   Returns list of name sorted references to Verilog::Netlist::Net in the interface.

       $self->nets_and_ports_sorted
	   Returns list of name sorted references to Verilog::Netlist::Net and Verilog::Netlist::Port in the interface.

       $self->ports
	   Returns list of references to Verilog::Netlist::Port in the interface.

       $self->ports_ordered
	   Returns list of references to Verilog::Netlist::Port in the interface sorted by pin number.

       $self->ports_sorted
	   Returns list of references to Verilog::Netlist::Port in the interface sorted by name.

MEMBER FUNCTIONS

       See also Verilog::Netlist::Subclass for additional accessors and methods.

       $self->find_net(name)
	   Returns Verilog::Netlist::Net matching given name.

       $self->level
	   Returns the reverse depth of this interface with respect to other modules and interfaces.  See also Netlist's modules_sorted_level.

       $self->lint
	   Checks the interface for errors.

       $self->link
	   Creates interconnections between this interface and other interfaces.

       $self->new_net
	   Creates a new Verilog::Netlist::Net.

       $self->dump
	   Prints debugging information for this interface.

       $self->verilog_text
	   Returns verilog code which represents this interface.  Returned as an array that must be joined together to form the final text string.
	   The netlist must be already ->link'ed for this to work correctly.

DISTRIBUTION

       Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA software tool suite.  The latest version is available from CPAN and
       from http://www.veripool.org/verilog-perl <http://www.veripool.org/verilog-perl>.

       Copyright 2000-2012 by Wilson Snyder.  This package is free software; you can redistribute it and/or modify it under the terms of either
       the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

AUTHORS

       Wilson Snyder <wsnyder@wsnyder.org>

SEE ALSO

       Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist

perl v5.14.2							    2012-05-04						   Netlist::Interface(3pm)

Check Out this Related Man Page

Netlist::Port(3pm)					User Contributed Perl Documentation					Netlist::Port(3pm)

NAME

       Verilog::Netlist::Port - Port for a Verilog Module

SYNOPSIS

	 use Verilog::Netlist;

	 ...
	 my $port = $module->find_port ('pinname');
	 print $port->name;

DESCRIPTION

       A Verilog::Netlist::Port object is created by Verilog::Netlist::Module for every port connection in the module.

ACCESSORS

       See also Verilog::Netlist::Subclass for additional accessors and methods.

       $self->array
	   Any array declaration for the port.	This only applies to Verilog 1995 style ports which can declare port bits independently from the
	   signal declarations.  When using Verilog 2001 style ports, see the matching net declaration's lsb and msb methods instead, for example
	   "$module-"find_net($port->name)->msb>.

       $self->comment
	   Returns any comments following the definition.  keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained.

       $self->data_type
	   The SystemVerilog data type of the port.

       $self->direction
	   The direction of the port: "in", "out", or "inout".

       $self->module
	   Reference to the Verilog::Netlist::Module the port is in.

       $self->name
	   The name of the port.

       $self->net
	   Reference to the Verilog::Netlist::Net the port connects to.  Only valid after the netlist is linked.

       $self->type
	   Approximately an alias of data_type for backward compatibility.  Do not use for new applications.

MEMBER FUNCTIONS

       See also Verilog::Netlist::Subclass for additional accessors and methods.

       $self->dump
	   Prints debugging information for this port.

DISTRIBUTION

       Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA software tool suite.  The latest version is available from CPAN and
       from http://www.veripool.org/verilog-perl <http://www.veripool.org/verilog-perl>.

       Copyright 2000-2012 by Wilson Snyder.  This package is free software; you can redistribute it and/or modify it under the terms of either
       the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

AUTHORS

       Wilson Snyder <wsnyder@wsnyder.org>

SEE ALSO

       Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist

perl v5.14.2							    2012-05-04							Netlist::Port(3pm)

Linux and UNIX Man Pages

verilog::netlist::interface(3pm) [debian man page]

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