arm_sync_icache(2) [netbsd man page]

ARM_SYNC_ICACHE(2)					    BSD/arm System Calls Manual 					ARM_SYNC_ICACHE(2)

NAME

     arm_sync_icache -- clean the CPU data cache and flush the CPU instruction cache

LIBRARY

     ARM Architecture Library (libarm, -larm)

SYNOPSIS

     #include <machine/sysarch.h>

     int
     arm_sync_icache(u_int addr, int len);

DESCRIPTION

     arm_sync_icache() will make sure that all the entries in the processor instruction cache are synchronized with main memory and that any data
     in a write back cache has been cleaned.  Some ARM processors (e.g. SA110) have separate instruction and data caches thus any dynamically gen-
     erated or modified code needs to be written back from any data caches to main memory and the instruction cache needs to be synchronized with
     main memory.

     On such processors arm_sync_icache() will clean the data cache and invalidate the processor instruction cache to force reloading from main
     memory.  On processors that have a shared instruction and data cache and have a write through cache (e.g. ARM6) no action needs to be taken.

     The routine takes a start address addr and a length len to describe the area of memory that needs to be cleaned and synchronized.

ERRORS

     arm_sync_icache() will never fail so will always return 0.

REFERENCES

     StrongARM Data Sheet

BSD
								  March 29, 2002							       BSD

sync_instruction_memory(3C)				   Standard C Library Functions 			       sync_instruction_memory(3C)

NAME

       sync_instruction_memory - make modified instructions executable

SYNOPSIS

       void sync_instruction_memory(caddr_t addr, int len);

DESCRIPTION

       The sync_instruction_memory() function performs whatever steps are required to make instructions modified by a program executable.

       Some  processor	architectures,	including  some  SPARC processors, have separate and independent instruction and data caches which are not
       kept consistent by hardware.  For example, if the instruction cache contains an instruction from some address and the program then stores a
       new  instruction  at  that  address,  the  new instruction may not be immediately visible to the instruction fetch mechanism. Software must
       explicitly invalidate the instruction cache entries for new or changed mappings of pages that might contain executable  instructions.   The
       sync_instruction_memory() function performs this function, and/or any other functions needed to make modified instructions between addr and
       addr+len visible. A program should call sync_instruction_memory() after modifying instructions and before executing them.

       On processors with unified caches (one cache for both instructions and data) and pipelines which are flushed by a branch instruction,  such
       as the x86 architecture, the function may do nothing and just return.

       The  changes  are  immediately  visible	to  the  thread calling sync_instruction_memory() when the call returns, even if the thread should
       migrate to another processor during or after the call. The changes become visible to other threads in the same manner that stores do;  that
       is, they eventually become visible, but the latency is implementation-dependent.

       The  result  of executing sync_instruction_memory() are unpredictable if addr through addr+len-1 are not valid for the address space of the
       program making the call.

RETURN VALUES

       No values are returned.

ATTRIBUTES

       See attributes(5) for descriptions of the following attributes:

       +-----------------------------+-----------------------------+
       |      ATTRIBUTE TYPE	     |	    ATTRIBUTE VALUE	   |
       +-----------------------------+-----------------------------+
       |MT-Level		     |MT-Safe			   |
       +-----------------------------+-----------------------------+

SEE ALSO

       attributes(5)

SunOS 5.11							    12 Feb 1997 				       sync_instruction_memory(3C)