Code:
ALOM BOOTMON v1.5.4
ALOM Build Release: 008
Reset register: e0000000 EHRS ESRS LLRS
ALOM POST 1.0
TTYD - Internal Loopback Test, PASSED.
Memory Data Lines Test
Memory Data Lines Test, PASSED.
Memory Address Lines Test
Slide address bits to test open address lines
Test for shorted address lines
Memory Address Lines Test, PASSED.
Memory Parity Test
Memory Parity Test, PASSED.
Boot Sector FLASH CRC Test
Boot Sector FLASH CRC Test, PASSED.
Return to Boot Monitor for Handshake
ALOM POST 1.0
Status = 00007fff
Returned from Boot Monitor and Handshake
Clearing Memory Cells
Memory Clean Complete
Loading the runtime image...
SC Alert: CRITICAL ALARM is set
SC Alert: SC System booted.
SC Alert: Input power unavailable for PSU @ PS0.
Sun(tm) Advanced Lights Out Manager 1.5.4 ()
Full VxDiag Tests
BASIC TOD TEST
Read the TOD Clock: SAT JAN 01 00:00:14 2000
Wait, 1 - 3 seconds
Read the TOD Clock: SAT JAN 01 00:00:16 2000
BASIC TOD TEST, PASSED
ETHERNET CPU LOOPBACK TEST
50 BYTE PACKET - a 0 in field of 1's. Attaching network interface cpm0... done.
50 BYTE PACKET - a 1 in field of 0's.
900 BYTE PACKET - pseudo-random data.
ETHERNET CPU LOOPBACK TEST, PASSED
Full VxDiag Tests - PASSED
Status summary - Status = 7FFF
VxDiag - - PASSED
POST - - PASSED
LOOPBACK - - PASSED
I2C - - PASSED
EPROM - - PASSED
FRU PROM - - PASSED
ETHERNET - - PASSED
MAIN CRC - - PASSED
BOOT CRC - - PASSED
TTYD - - PASSED
TTYC - - PASSED
MEMORY - - PASSED
MPC850 - - PASSED
Please login: admin
Please Enter password: *********
sc> poweron
SC Alert: Host System has Reset
SC Alert: CRITICAL ALARM is set
sc> setalarm critical off
sc> break -y
sc>
SC Alert: SC Request to send Break to host.
sc> show
SC Alert: VOLTAGE_SENSOR @ MB.BAT.V_BAT has exceeded low warning threshold.
Invalid command. Type 'help' for list of commands.
sc> showfru
FRU_PROM at MB.SEEPROM
Manufacturer Record
Timestamp: MON JUL 03 10:05:20 UTC 2006
Description: FRUID,INSTR,M'BD,2X1.5GHZ,CPU
Manufacture Location: Shunde,China
Sun Part No: 3753227
Sun Serial No: S6006P
Vendor JEDEC code: 3E5
Initial HW Dash Level: 03
Initial HW Rev Level: 05
Shortname: MOTHERBOARD
FRU_PROM at ENC.SEEPROM
Manufacturer Record
Timestamp: TUE MAR 14 00:14:42 UTC 2006
Description: FRUID,PRGM,INSTR,2U,IN/FACE,LOW
Manufacture Location: Hsinchu,Taiwan
Sun Part No: 3706004
Sun Serial No: H019RV
Vendor JEDEC code: 3E5
Initial HW Dash Level: 03
Initial HW Rev Level: 0E
Shortname: SCSI
FRU_PROM at HCM.SEEPROM is not present
FRU_PROM at PS0.SEEPROM
Manufacturer Record
Timestamp: TUE MAR 21 03:15:47 UTC 2006
Description: ASY,PSU,EN-2U,400W,D158,ROHS
Manufacture Location: BAO'AN, CHINA
Sun Part No: 3001845
Sun Serial No: 007173
Vendor JEDEC code: 37A
Initial HW Dash Level: 01
Initial HW Rev Level: 50
Shortname: PS
FRU_PROM at PS1.SEEPROM
Manufacturer Record
Timestamp: TUE MAR 21 03:18:05 UTC 2006
Description: ASY,PSU,EN-2U,400W,D158,ROHS
Manufacture Location: BAO'AN, CHINA
Sun Part No: 3001845
Sun Serial No: 007175
Vendor JEDEC code: 37A
Initial HW Dash Level: 01
Initial HW Rev Level: 50
Shortname: PS
FRU_PROM at ALARM.SEEPROM is not present
FRU_PROM at MB.P0.B0.D0.SEEPROM
Timestamp: MON JAN 30 12:00:00 UTC 2006
Description: SDRAM DDR, 1024 MB
Manufacture Location:
Vendor: Infineon (formerly Siemens)
Vendor Part No: 72D128320GBR6C
FRU_PROM at MB.P0.B0.D1.SEEPROM
Timestamp: MON DEC 26 12:00:00 UTC 2005
Description: SDRAM DDR, 1024 MB
Manufacture Location:
Vendor: Infineon (formerly Siemens)
Vendor Part No: 72D128320GBR6C
FRU_PROM at MB.P0.B1.D0.SEEPROM is not present
FRU_PROM at MB.P0.B1.D1.SEEPROM is not present
FRU_PROM at MB.P1.B0.D0.SEEPROM is not present
FRU_PROM at MB.P1.B0.D1.SEEPROM is not present
FRU_PROM at MB.P1.B1.D0.SEEPROM is not present
FRU_PROM at MB.P1.B1.D1.SEEPROM is not present
sc>
SC Alert: ENCLOSURE_FAN @ F2.RS has FAILED.
sc> console
Enter #. to return to ALOM.
0>Setup L2 Cache
0>L2 Cache Control = 00000000.00f04400
0> Size = 00000000.00100000...
0>Setup and Enable DMMU
0>Setup DMMU Miss Handler
0>Scrub Mailbox
0>Timing is 9:1 12:1, sys 167 MHz, CPU 1504 MHz, mem 125 MHz.
0> UltraSPARC[TM] IIIi, Version 3.4
1>Init CPU
1> UltraSPARC[TM] IIIi, Version 3.4
1>Init mmu regs
1>Setup L2 Cache
1>L2 Cache Control = 00000000.00f04400
1> Size = 00000000.00100000...
1>Setup and Enable DMMU
1>Setup DMMU Miss Handler
1>Scrub Mailbox
1>Timing is 9:1 12:1, sys 167 MHz, CPU 1504 MHz, mem 125 MHz.
0>Init Memory.....
0>Probe Dimms
1>Probe Dimms
1>Init Mem Controller Sequence
0>Init Mem Controller Sequence
0>IO-Bridge unit 0 init test
0>IO-Bridge unit 1 init test
0>Test Memory.....
0>Select Bank Config
0>Probe and Setup Memory
0>INFO: 1024MB Bank 0, Dimm Type X4
0>INFO: 1024MB Bank 1, Dimm Type X4
0>INFO: No memory detected in Bank 2
0>INFO: No memory detected in Bank 3
0>
0>Data Bitwalk on Master
0> Test Bank 0.
0>
0>ERROR: TEST = Data Bitwalk on Master
0>H/W under test = CPU0 Memory
0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0>MSG = Incorrect syndrome 00000000.000000d8. Not a single bit CE
0>END_ERROR
0>
0>ERROR: TEST = Data Bitwalk on Master
0>H/W under test = MB/P0/B0/D0 (Bank 0), Motherboard
0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0>MSG = Pin 114 failed on MB/P0/B0/D0 (Bank 0), Motherboard
0>END_ERROR
0>
0>ERROR: TEST = Data Bitwalk on Master
0>H/W under test = MB/P0/B0/D0 (Bank 0), Motherboard
0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0>MSG = Pin 117 failed on MB/P0/B0/D0 (Bank 0), Motherboard
0>END_ERROR
0>
0>ERROR: TEST = Data Bitwalk on Master
0>H/W under test = MB/P0/B0/D0 (Bank 0), Motherboard
0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0>MSG = ERROR: miscompare on mem test!
Address: 00000000.001b0040
Expected: ffffffff.ffffffff
Observed: ffffcfff.ffffffff
0>END_ERROR
0> Test Bank 1.
0>
0>ERROR: TEST = Data Bitwalk on Master
0>H/W under test = MB/P0/B0/D1 (Bank 1), Motherboard
0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0>MSG = Pin 171 failed on MB/P0/B0/D1 (Bank 1), Motherboard
0>END_ERROR
0>
0>ERROR: TEST = Data Bitwalk on Master
0>H/W under test = MB/P0/B0/D0 (Bank 1), Motherboard
0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0>MSG = Pin 45 failed on MB/P0/B0/D0 (Bank 1), Motherboard
0>END_ERROR
0>
0>ERROR: TEST = Data Bitwalk on Master
0>H/W under test = MB/P0/B0/D0 (Bank 1), Motherboard
0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0>MSG = Pin 49 failed on MB/P0/B0/D0 (Bank 1), Motherboard
0>END_ERROR
0>
0>ERROR: TEST = Data Bitwalk on Master
0>H/W under test = MB/P0/B0/D0 (Bank 1), Motherboard
0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0>MSG = ERROR: miscompare on mem test!
Address: 00000001.001b0000
Expected: 00000000.00000001
Observed: 008f00ff.00ff00ff
0>END_ERROR
0>
0>ERROR: TEST = Data Bitwalk on Master
0>H/W under test = CPU0 Memory
0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0>MSG =
*** Test Failed!! ***
0>END_ERROR
0>
0>ERROR: TEST = Data Bitwalk on Master
0>H/W under test = CPU0 Memory
0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0>MSG = No good memory available on master CPU 0, rolling over to new Master.
0>END_ERROR
1>Soft Power-on RST thru SW
1>OBP->POST Call with %o0=00001000.01014000.
1>Diag level set to MAX.
1>Verbosity level set to MAX.
1>MFG scrpt mode set NORM
1>I/O port set to TTYA.
1>Start Selftest.....
1>CPUs present in system: 0 1
1>Test CPU(s).....
1>Init SB
1>Initialize I2C Controller
1>Init CPU
1>DMMU
1>DMMU TLB DATA RAM Access
1>DMMU TLB TAGS Access
1>IMMU Registers Access
1>IMMU TLB DATA RAM Access
1>IMMU TLB TAGS Access
1>Init mmu regs
1>Setup L2 Cache
1>L2 Cache Control = 00000000.00f04400
1> Size = 00000000.00100000...
1>L2 Cache Tags Test
1>Scrub and Setup L2 Cache
1>Setup and Enable DMMU
1>Setup DMMU Miss Handler
1>Test Mailbox
1>Scrub Mailbox
1>CPU Tick and Tick Compare Registers Test
1>CPU Stick and Stick Compare Registers Test
1>Set Timing
1> UltraSPARC[TM] IIIi, Version 3.4
0>Init CPU
0> UltraSPARC[TM] IIIi, Version 3.4
0>DMMU
0>DMMU TLB DATA RAM Access
0>DMMU TLB TAGS Access
0>IMMU Registers Access
0>IMMU TLB DATA RAM Access
0>IMMU TLB TAGS Access
0>Init mmu regs
0>Setup L2 Cache
0>L2 Cache Control = 00000000.00f04400
0> Size = 00000000.00100000...
0>L2 Cache Tags Test
0>Scrub and Setup L2 Cache
0>Setup and Enable DMMU
0>Setup DMMU Miss Handler
0>Test Mailbox
0>Scrub Mailbox
0>CPU Tick and Tick Compare Registers Test
0>CPU Stick and Stick Compare Registers Test
1>Interrupt Crosscall.....
0>Setup Int Handlers
1>Setup Int Handlers
1>Send Int CPU 0
0>Send Int to Master CPU
1>MB: Part-Dash-Rev#: 3753227-03-05 Serial#: S6006P
1>CPU0 MB/P0/B0/D0:
1>Part#: 72D128320GBR6C Serial#: 03169923 Date Code: 0605 Rev#: 042c
1>CPU0 MB/P0/B0/D1:
1>Part#: 72D128320GBR6C Serial#: 04063c24 Date Code: 0550 Rev#: 042c
1>Set CPU/System Speed
1>Jumper data = 3a
1>..
1>Send MC Timing CPU 0
1>Init Memory.....
1>Probe Dimms
0>Probe Dimms
0>Init Mem Controller Regs
1>Init Mem Controller Regs
0>Set JBUS config reg
1>Set JBUS config reg
1>IO-Bridge unit 0 init test
1>IO-Bridge unit 1 init test
1>Do PLL reset
1>Setting timing to 9:1 12:1, system frequency 167 MHz, CPU frequency 1503 MHz
1>Soft Power-on RST thru SW
1>PLL Reset.....
1>Init SB
1>Initialize I2C Controller
1>Init CPU
1>Init mmu regs
1>Setup L2 Cache
1>L2 Cache Control = 00000000.00f04400
1> Size = 00000000.00100000...
1>Setup and Enable DMMU
1>Setup DMMU Miss Handler
1>Scrub Mailbox
1>Timing is 9:1 12:1, sys 167 MHz, CPU 1504 MHz, mem 125 MHz.
1> UltraSPARC[TM] IIIi, Version 3.4
0>Init CPU
0> UltraSPARC[TM] IIIi, Version 3.4
0>Init mmu regs
0>Setup L2 Cache
0>L2 Cache Control = 00000000.00f04400
0> Size = 00000000.00100000...
0>Setup and Enable DMMU
0>Setup DMMU Miss Handler
0>Scrub Mailbox
0>Timing is 9:1 12:1, sys 167 MHz, CPU 1504 MHz, mem 125 MHz.
1>Init Memory.....
1>Probe Dimms
0>Probe Dimms
0>Init Mem Controller Sequence
1>Init Mem Controller Sequence
1>IO-Bridge unit 0 init test
1>IO-Bridge unit 1 init test
1>Test Memory.....
1>Select Bank Config
1>Probe and Setup Memory
1>
1>INFO: No memory on cpu 1
1>
1>ERROR: TEST = Probe and Setup Memory
1>H/W under test = CPU1 Memory
1>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1>MSG = No good memory available on master CPU 1, rolling over to new Master.
1>END_ERROR
1>ERROR:
1> POST toplevel status has the following failures:
1> MB/P0/B0/D0 (Bank 0), Motherboard
1> MB/P0/B0/D0 (Bank 1), Motherboard
1> MB/P0/B0/D1 (Bank 1), Motherboard
1>END_ERROR
1>
1>ERROR: No good CPUs OR CPUs with good memory left. Calling debug menu
SC Alert: MB/P0/B0/D0 (Bank 0), Motherboard has been failed by POST
SC Alert: MB/P0/B0/D0 (Bank 1), Motherboard has been failed by POST
SC Alert: MB/P0/B0/D1 (Bank 1), Motherboard has been failed by POST
.
1> 0 Peek/Poke interface
1> 1 Dump CPU Regs
1> 2 Dump Valid L2$
1> 3 Dump Trap Table
1> 4 Dump Mem Controller Regs
1> 5 Dump Valid DMMU entries
1> 6 Dump IMMU entries
1> 7 Dump Mailbox
1> 8 Dump IO-Bridge regs
1> 9 Allow other CPUs to print
1> a Do soft reset
1> ? Help
1>
1>Selection:1
1>PState = 00000000.00000016
1>AFSR = 00000000.00000000
1> No Errors in afsr reg
1>AFAR = 00000000.00000000
1>Dispatch Control =00000000.00001a3f
1>Data Cache Unit Control =0000c400.00000008
1>IMMU SFSR = 00000000.00000000
1>DMMU SFSR = 00000000.00000000
1>DMMU SFAR = 00000010.0008ec00
1>EState = 00000000.00000000
1>Default Globals:
1> g1 = 00000000.3ffffc00.
1> g2 = ffffffff.c0000000.
1> g3 = fffff800.00000000.
1> g4 = 000007ff.ffffffff.
1> g5 = 00000400.0f600000.
1> g6 = 00400400.10002000.
1> g7 = 00040000.00000000.
1>MMU Globals:
1> g1 = 00000000.00000000.
1> g2 = 00000000.00000000.
1> g3 = ffffffff.f00560c0.
1> g4 = ffffffff.00000000.
1> g5 = 00000000.00000068.
1> g6 = 00000000.00000000.
1> g7 = 00000020.00000000.
1>Alternate Globals:
1> g1 = 00000000.00000000.
1> g2 = 00000000.00000000.
1> g3 = ffffffff.f007fb20.
1> g4 = ffffffff.00000000.
1> g5 = 00000000.000000ff.
1> g6 = 00000000.00000000.
1> g7 = 504f5354.afb0acab.
1>Interrupt Globals:
1> g1 = 00000000.00000101.
1> g2 = ffffffff.f00707a0.
1> g3 = 00000000.00000000.
1> g4 = ffffffff.00000000.
1> g5 = 00000000.00000000.
1> g6 = 00000000.00000000.
1> g7 = 00000000.00002000.
1>cwp = 00000000.00000001.
1>cansave = 00000000.00000005.
1>canrestore = 00000000.00000001.
1>cleanwin = 00000000.00000005.
1>otherwin = 00000000.00000000.
1>sp = ffffffff.fffffe9f.
1> 00000000.00000000 Soft Interrupt
1>Serial ID = 0000005b.b3e62467
1> 0 Peek/Poke interface
1> 1 Dump CPU Regs
1> 2 Dump Valid L2$
1> 3 Dump Trap Table
1> 4 Dump Mem Controller Regs
1> 5 Dump Valid DMMU entries
1> 6 Dump IMMU entries
1> 7 Dump Mailbox
1> 8 Dump IO-Bridge regs
1> 9 Allow other CPUs to print
1> a Do soft reset
1> ? Help
1>
1>Selection:4
1>JBUS config reg = 03fb3ffe.104201ee.
1>L2Cache CSR reg = 00000000.00f14000.
1>mc timing 1 = f0000002.3e481c1e.
1>mc timing 2 = 0000569b.49009028.
1>mc timing 3 = 00000000.00010001.
1> 0 Peek/Poke interface
1> 1 Dump CPU Regs
1> 2 Dump Valid L2$
1> 3 Dump Trap Table
1> 4 Dump Mem Controller Regs
1> 5 Dump Valid DMMU entries
1> 6 Dump IMMU entries
1> 7 Dump Mailbox
1> 8 Dump IO-Bridge regs
1> 9 Allow other CPUs to print
1> a Do soft reset
1> ? Help
1>
1>Selection:5
1> Small TLB
1>Entry Tag Data
1>00000000.00000000 ffffffff.f0000000 e00007ff.f0000041
1>00000000.00000008 000007ff.f0000000 e00007ff.f0000041
1>00000000.00000010 f0000000.00000000 c0000010.00080063
1>00000000.00000018 00000400.0f602040 80000400.0f602043
1>00000000.00000020 00000400.0e602040 80000400.0e602043
1>00000000.00000028 00000010.0008efff e0000010.0008e023
1> 8K TLB 0
1>Entry Tag Data
1> 8K TLB 1
1>Entry Tag Data
1> 0 Peek/Poke interface
1> 1 Dump CPU Regs
1> 2 Dump Valid L2$
1> 3 Dump Trap Table
1> 4 Dump Mem Controller Regs
1> 5 Dump Valid DMMU entries
1> 6 Dump IMMU entries
1> 7 Dump Mailbox
1> 8 Dump IO-Bridge regs
1> 9 Allow other CPUs to print
1> a Do soft reset
1> ? Help
1>
1>Selection:7
1>Mailbox start address f0000000.00000000.
1>CPU 0 mem struct start address f0000000.00000080.
1> mem_segment start address f0000000.00000080.
1> mem empty f0000000.00000240=-443897921.
1> mem fail f0000000.00000248=16776960.
1> start address bank 0 f0000000.000000a0=dfbf0000.002cffff.
1> end address bank 0= f0000000.000000c0=00bf0000.0000ff00.
1> size bank 0 f0000000.000000e0=00bf0000.0000ffbe.
1> remaining mem bank 0 f0000000.00000100=00bf0000.002cffbe.
1> bank status mem bank 0 f0000000.00000120=dfbf0000.0000ffbe.
1> bank valid mem bank 0 f0000000.00000080=dfbf0000.002cffbe.
1> dimm size bank 0 dimm 0 f0000000.00000160=dfbf0000.000000bc.
1> dimm size bank 0 dimm 1 f0000000.00000168=f71aeae5.00ff04ee.
1> start address bank 1 f0000000.000000a8=f7feffff.fe0000ff.
1> end address bank 1= f0000000.000000c8=f71affe7.fedf00ee.
1> size bank 1 f0000000.000000e8=f7ffffff.fe0000fe.
1> remaining mem bank 1 f0000000.00000108=f71aefe7.fc9d00ee.
1> bank status mem bank 1 f0000000.00000128=f51aeae5.7cff00ec.
1> bank valid mem bank 1 f0000000.00000088=f7fe7fff.fe0000fe.
1> dimm size bank 1 dimm 0 f0000000.00000170=00fff500.002cffbe.
1> dimm size bank 1 dimm 1 f0000000.00000178=fffeeec7.fe9ceeee.
1> start address bank 2 f0000000.000000b0=00fff500.3f2cffff.
1> end address bank 2= f0000000.000000d0=00fff500.2f2cffff.
1> size bank 2 f0000000.000000f0=00fff500.2d2cffbf.
1> remaining mem bank 2 f0000000.00000110=00fff5ef.3f00ffff.
1> bank status mem bank 2 f0000000.00000130=00bff467.0d2cffff.
1> bank valid mem bank 2 f0000000.00000090=cbbfffef.ff00ffff.
1> dimm size bank 2 dimm 0 f0000000.00000180=00bff5ef.3f2cffff.
1> dimm size bank 2 dimm 1 f0000000.00000188=f7feffff.fedf00fe.
1> start address bank 3 f0000000.000000b8=f7daea45.7c0000ec.
1> end address bank 3= f0000000.000000d8=f700eac5.7cff00ec.
1> size bank 3 f0000000.000000f8=ff00eec7.fedf00ee.
1> remaining mem bank 3 f0000000.00000118=fffeeee7.fe9f00ec.
1> bank status mem bank 3 f0000000.00000138=f7daeac7.fcddeeee.
1> bank valid mem bank 3 f0000000.00000098=f7daeac5.7c9ceeee.
1> dimm size bank 3 dimm 0 f0000000.00000190=00fff500.002cffff.
1> dimm size bank 3 dimm 1 f0000000.00000198=ff00eeef.fe00ee00.
1> lock bit f0000000.000003a0=0.
1> malloc table address = f0000000.000003a8.
1> stack ptr = f0000000.00001368
1> user input = f0000000.0000eb68
1>CPU 1 mem struct start address f0000000.0000ec00.
1> mem_segment start address f0000000.0000ec00.
1> mem empty f0000000.0000edc0=1.
1> mem fail f0000000.0000edc8=0.
1> start address bank 0 f0000000.0000ec20=00000000.00000000.
1> end address bank 0= f0000000.0000ec40=00000000.00000000.
1> size bank 0 f0000000.0000ec60=00000000.00000000.
1> remaining mem bank 0 f0000000.0000ec80=00000000.00000000.
1> bank status mem bank 0 f0000000.0000eca0=00000000.00000000.
1> bank valid mem bank 0 f0000000.0000ec00=00000000.00000000.
1> dimm size bank 0 dimm 0 f0000000.0000ece0=00000000.00000000.
1> dimm size bank 0 dimm 1 f0000000.0000ece8=00000000.00000000.
1> start address bank 1 f0000000.0000ec28=00000000.00000000.
1> end address bank 1= f0000000.0000ec48=00000000.00000000.
1> size bank 1 f0000000.0000ec68=00000000.00000000.
1> remaining mem bank 1 f0000000.0000ec88=00000000.00000000.
1> bank status mem bank 1 f0000000.0000eca8=00000000.00000000.
1> bank valid mem bank 1 f0000000.0000ec08=00000000.00000000.
1> dimm size bank 1 dimm 0 f0000000.0000ecf0=00000000.00000000.
1> dimm size bank 1 dimm 1 f0000000.0000ecf8=00000000.00000000.
1> start address bank 2 f0000000.0000ec30=00000000.00000000.
1> end address bank 2= f0000000.0000ec50=00000000.00000000.
1> size bank 2 f0000000.0000ec70=00000000.00000000.
1> remaining mem bank 2 f0000000.0000ec90=00000000.00000000.
1> bank status mem bank 2 f0000000.0000ecb0=00000000.00000000.
1> bank valid mem bank 2 f0000000.0000ec10=00000000.00000000.
1> dimm size bank 2 dimm 0 f0000000.0000ed00=00000000.00000000.
1> dimm size bank 2 dimm 1 f0000000.0000ed08=00000000.00000000.
1> start address bank 3 f0000000.0000ec38=00000000.00000000.
1> end address bank 3= f0000000.0000ec58=00000000.00000000.
1> size bank 3 f0000000.0000ec78=00000000.00000000.
1> remaining mem bank 3 f0000000.0000ec98=00000000.00000000.
1> bank status mem bank 3 f0000000.0000ecb8=00000000.00000000.
1> bank valid mem bank 3 f0000000.0000ec18=00000000.00000000.
1> dimm size bank 3 dimm 0 f0000000.0000ed10=00000000.00000000.
1> dimm size bank 3 dimm 1 f0000000.0000ed18=00000000.00000000.
1> lock bit f0000000.0000ef20=0.
1> malloc table address = f0000000.0000ef28.
1> stack ptr = f0000000.0000fee8
1> user input = f0000000.0001d6e8
1> 0 Peek/Poke interface
1> 1 Dump CPU Regs
1> 2 Dump Valid L2$
1> 3 Dump Trap Table
1> 4 Dump Mem Controller Regs
1> 5 Dump Valid DMMU entries
1> 6 Dump IMMU entries
1> 7 Dump Mailbox
1> 8 Dump IO-Bridge regs
1> 9 Allow other CPUs to print
1> a Do soft reset
1> ? Help
1>
1>Selection:8
1>
1>FATAL ERROR!!
1>ERROR: Unexpected Watchdog!
1>Decode of afsr bits 00301006.00000125
1> ME Bit: Multiple errors of same type occured.
1> PRIV Bit: Privileged code access error(s) has occured.
1> TO Bit: Unmapped error from JBUS
1> UE Bit: Uncorrectable data bus ECC error from memory
1> CE Bit: Correctable data bus ECC error from memory
1> Data ECC Syndrome = 00000125
1>
1>AFAR 00000010.00080240
1>JBUS config reg = 03fb3ffe.104201ee.
1>L2Cache CSR reg = 00000000.00f14000.
1>Tom 0 JBUS CSR 00090bf9.31c00000
1>Tom 0 JBUSUE reg 00000000.1c000000
1>Tom 0 JBUSCE reg 00000000.1c000000
1>Tom 0 JBUS Error log reg 00000000.00000000
1>Tom 1 JBUS CSR 000903f5.11e00000
1>Tom 1 JBUSUE reg 00000000.1e000000
1>Tom 1 JBUSCE reg 00000000.1e000000
1>Tom 1 JBUS Error log reg 00000000.00000000
1>
SC Alert: MB/P0/B0/D0 (Bank 0), Motherboard has been failed by POST
SC Alert: MB/P0/B0/D0 (Bank 1), Motherboard has been failed by POST
SC Alert: MB/P0/B0/D1 (Bank 1), Motherboard has been failed by POST
SC Alert: MB/P0/B0/D0 (Bank 0), Motherboard has been failed by POST
SC Alert: MB/P0/B0/D0 (Bank 1), Motherboard has been failed by POST
SC Alert: MB/P0/B0/D1 (Bank 1), Motherboard has been failed by POST
SC Alert: MB/P0/B0/D0 (Bank 0), Motherboard has been failed by POST
SC Alert: MB/P0/B0/D0 (Bank 1), Motherboard has been failed by POST
SC Alert: MB/P0/B0/D1 (Bank 1), Motherboard has been failed by POST
SC Alert: MB/P0/B0/D0 (Bank 0), Motherboard has been failed by POST
SC Alert: MB/P0/B0/D0 (Bank 1), Motherboard has been failed by POST
1> 0 Peek/Poke interface
SC Alert: MB/P0/B0/D1 (Bank 1), Motherboard has been failed by POST
1> 1 Dump CPU Regs
SC Alert: MB/P0/B0/D0 (Bank 0), Motherboard has been failed by POST
1> 2 Dump Valid L2$
SC Alert: MB/P0/B0/D0 (Bank 1), Motherboard has been failed by POST
SC Alert: MB/P0/B0/D1 (Bank 1), Motherboard has been failed by POST
1> 3 Dump Trap Table
SC Alert: MB/P0/B0/D0 (Bank 0), Motherboard has been failed by POST
1> 4 Dump Mem Controller Regs
SC Alert: MB/P0/B0/D0 (Bank 1), Motherboard has been failed by POST
SC Alert: MB/P0/B0/D1 (Bank 1), Motherboard has been failed by POST
1> 5 Dump Valid DMMU ent
SC Alert: MB/P0/B0/D0 (Bank 0), Motherboard has been failed by POST
ries
1> 6 Dump IMMU entries
SC Alert: MB/P0/B0/D0 (Bank 1), Motherboard has been failed by POST
SC Alert: MB/P0/B0/D1 (Bank 1), Motherboard has been failed by POST
1> 7 Dump Mailbo
SC Alert: MB/P0/B0/D0 (Bank 0), Motherboard has been failed by POST
x
1> 8 Dump IO-Bridge regs
SC Alert: MB/P0/B0/D0 (Bank 1), Motherboard has been failed by POST
SC Alert: MB/P0/B0/D1 (Bank 1), Motherboard has been failed by POST
1> 9 Allow other CPUs to print
1> a Do soft reset
1> ? Help
1>
1>Selection: